In the processing of information generally, it often is necessary to compare two different signals to accomplish a variety of purposes. The comparison may result in the generation of an error signal representing a difference between the two signals. Circuitry may then respond to the error signal to minimize this difference between the two signals or perform some other function based on this difference, as is needed.
For example, a phase detector is conventionally used to detect the difference in phase between two signals. The phase detector may be used in a phase-locked loop that, among other components, has a voltage controlled oscillator (VCO) whose output is a reference frequency signal having a stream of frequency pulse signals. The phase detector receives a stream of data pulse signals, together with the frequency pulse signals which are fed back from the VCO. Any difference in phase between the data pulse signals and the frequency pulse signals results in the generation of a phase error signal that is filtered and then used to control the VCO so that the frequency pulse signals and the data pulse signals become in phase.
Certain types of data pulse streams, such as those known as MFM disk data, can cause difficulty when inputted to a phase-locked loop via the phase detector. This is because the data pulse stream will have "holes" in it, meaning that there are no data pulse signals in the pulse stream for a given period, such as a "bit time" if the data pulse signals are binary digital signals. As is known, these "missing" data pulse signals can cause the phase detector to malfunction.
A prior approach to avoiding malfunction due to missing data pulse signals is to arm the phase detector only if a data pulse signal occurs and to disarm the phase detector if a data pulse signal does not occur during the bit time. This technique uses a time delay device which receives in real time the stream of data pulse signals and outputs to the phase detector delayed data pulse signals which are to be compared to the frequency pulse signal of the VCO. The phase detector also receives in real time the stream of data pulse signals for arming purposes.
Thus, in operation, the data pulse stream is fed to the input of the time delay device as well as to the phase detector. If a data pulse signal occurs, the phase detector is armed and then, a short time later, receives the same, but delayed, data pulse signal which had been delayed by the time delay device. This delayed data pulse signal is then compared with the frequency pulse signal to produce the phase error signal. However, if no data pulse signal occurs during the bit time, the phase detector is not armed, so that it does not operate for phase detection purposes.
One problem with the prior solution is the requirement of a time delay device. In addition to requiring a time delay device which may be expensive, the delay must be precise, so as to have the phase detector properly compare its two input signals. The realization of such a precision time delay is not always easily accomplished. Also, the delay should be equal to one-half the cycle of the nominal frequency of the VCO. Therefore, if the nominal frequency of the VCO is to be changed, which may require using a different VCO in the phase-locked loop, then a new time delay device may be needed in view of the requirement that the delay be equal to one-half the cycle of the nominal frequency. Still furthermore, the arming and disarming of the phase detector has the disadvantage of causing the phase detector to change state between an operative or armed condition and a non-operative or disarmed condition.
In certain applications of a phase detector, such as in many phase-locked loop systems, it is desirable to maintain the output signal at a level corresponding to an integral of the existing phase error between the two signals in real time for each cycle in which a data pulse occurs. The related U.S. patent application entitled "PHASE DETECTOR" referred to above discloses one circuit for generating such an output signal. Furthermore, the related application discloses an invention which overcomes many of the problems of the above-mentioned prior art phase detectors. The present invention provides an improvement in the phase detector claimed in the related application.